Timing Reciever Card Information

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This is an attempt to archive some documentation on the Far Detector Timing Reciever cards. These cards are designed by Colin Perry.

Issue B Caldet boards, June 12 2003

here are some notes on using the new Issue B TRCs for the CalDet ND/FD
tests.

Note that all 4 TRCs (#6 to #9 inclusive) are identically configured,
and programmed with the file 'trc_a_2.mcs'.


CONNECTORS

RJ45 sockets, from top down:
    J180 (LVDS IN)  :  timing input on slave in a two crate system
    J181 (LVDS OUT #1) : output from master to ND timing system (40MHz
and 1 second)
    J182 (LVDS OUT #2) : timing output to slave in a two crate system
    J183 and J184 (LVDS OUT #3 and #4) duplicate J182 and are not
required.

LEMO sockets, from top down
    J195 (TTL OUT #3) : second signal, TTL square wave (reference for
investigating synchronization between FD and ND systems, as provided for
Argonne tests).
    J194 (TTL OUT #2) : veto pulse about buffer swap, positive TTL
pulse, 1ms either side of swap.


SWITCHES

SW360 (left or front): set master/slave mode and IRQ level.  Unchanged
from previous usage:
    1..7 sets master mode, IRQ 1 to 7
    9..F sets slave mode, IRQ 1 to 7.
SW361 (right or rear):
    Master mode: sets form of output to ND timing system, unchanged from
Argonne test board:
        0: base configuration:
            40MHz clock on pins (7,8), second on pins (1,2)
            Second signal a square wave (goes high at second)   
            Default polarity for the two signals: positive or high
outputs on pins 1 and 7.
        +8: swap clock and second to pairs (1,2) and (7,8)
        +4: change second to a 25ns pulse
        +2: invert signal to pair (1,2)
        +1: invert signal to pair (7,8)
    Slave mode: sets delay to backplane timing output, increasing in
steps of 12.5ns from approximately 40ns to 225ns for '0' to 'F'.  This
is relative to the second output as sent to the ND system and the
reference output on J195.  Note that the master has a fixed delay to its
backplane outputs of approximately 225ns: ie master and slave outputs
should match if they are connected by a zero length cable. (This differs
from the Argonne test version).


JUMPERS

The jumper on J600 has to be set to match the required IRQ level; it is
supplied set to '1'.  Other jumper settings are as before, and should
not require changing.

CalDet / Near Detector Interface TRC

Notes from Colin about a TRC prototype used for ND/FD interface at Argonne and CalDet.
TRC: Argonne Version for CalDet
ND/FD Timing Integration Tests
C.Perry 07apr02

1. Hardware

The TRC is a essentially the same as the Soudan TRCs, a version B board with the same basic component fit. There are the following differences:

a) Two RJ45 jacks are fitted at the front, one for LVDS output, and one input. (The Soudan boards have either four outputs and one input, or just the one input). Only the output jack should be used (the lower position RJ45, identified on board legend). The input was fitted only for test purposes.

b) The LVDS outputs to the front panel have had their DC isolating capacitors bridged with zero-ohm links. In normal master-slave operation the outputs work at 50% duty factor, and blocking DC gives immunity to low frequency (eg mains) common mode voltages between crates. This is not permissible in this case, with an unencoded 'second' signal.

c) A LEMO connector has been fitted on a TTL output to provide a convenient timing reference for tests. This is the same connector used at CalDet for the 'inhibit' output about buffer swaps, but used for a different purpose.

d) The 40MHz crystal oscillator has been checked, and found to be about 4ppm high in frequency (in a moderately warm lab ambient). This should be well within the lock range of the Argonne VCXOs. Note however that it is a low qualtity oscillator, and will show a moderate amount of jitter over long periods. I have measured about 1ns rms over periods of around 1ms (some of which may be coming from my 'scope); it is much better over shorter periods.

2. Firmware

Board is loaded with trc_a_1.mcs. This is based on the current Soudan firmware (trc_s_2.mcs) with limited changes. Except as noted, all settings and commands are unaffected.

a) The 40MHz clock and the second signal which are used to drive the backplane are also put on the front panel LVDS output RJ45 jack.

Defaults with right hex switch at 0 are:
'second': +ve pin 1, -ve pin 2 square wave, +ve going edge at second
'40MHz': +ve pin 7, -ve pin 8 +ve going edge at transitions of 'second'
'unused 1': +ve pin 4, -ve pin 5 driven low
'unused 2': +ve pin 3, -ve pin 6, driven low

These are modified by the right-hand hex switch:
bit 0 (add 1) invert signal on pins (7,8) ('40MHz' in default state)
bit 1 (add 2) invert signal on pins (1,2) ('second' in default state)
bit 2 (add 4) change 'second' to a 25ns +ve pulse, leading edge on second
bit 3 (add 8) exchange signals between (1,2) and (7,8)

b) Delay on backplane output in 'master' mode is fixed at '8', and is no longer controlled by the right hex switch.

c) A one second square wave, identical in timing with the LVDS front panel 'second' output signal, is put on the TTL output at the front LEMO connector.

d) It should be used with the TRC set to 'master': ie the left hand hex switch set in the range 1..7, to the required VME interrupt level.

Older Notes: (These notes are for old revisions of the timing cards, not the new optical cards. I leave this here as a reference)

Nov 30, 2001:

New firmare installed at Soudan, with these notes and this binary file.

Aug 10, 2001: TRC instructions

PROGRAMMING INSTRUCTIONS

Make sure there is a jumper fitted in the 'front' position on J361; the
ROM can then be programmed from the front header J191 with either my
cable or the standard Xilinx flying leads.

For the FPGA to configure correctly, make sure the jumper is fitted in
the 'use XC18' position, and in the mode pin positions 'M0' and 'M1'
(formerly 'M2' was also specified, but this is not required).

The upper front panel push button SW190 will cause the FPGA to
reconfigure if the jumper if fitted to JP104 in the lower position.

BASIC STAND ALONE INSTALLATION/OPERATING INSTRUCTIONS

Set the left hex switch (SW360) to the required VME interrupt level.
Set the jumper on J600 to match: the top postion is for IRQ7, down to
IRQ1 at 3 up from the bottom (as supplied).

Set the right hex switch (SW361) to 0.

The board should power up with the upper LED (D191) off, and the lower
one (D190) flashing in half second bursts at the swap frequency.

The top nibble of the VME interrupt vector is hex E. The bottom nibble
is the interrupt level, with 0 or 1 appended as the bottom bit,
alternating on successive interrupts. Ie for IRQ7, the vectors are
11101110/11101111.

Pressing the lower button (SW191) will cause a burst of 100 executes, at
10ms intervals, to be generated. The upper LED will come on for the 1
sec duration of the burst.

Setting switch SW361 to 8 causes the board to power up set to continuous
executes (rather than burst mode). This is initially off, and is
toggled by the lower button. State is shown by the upper LED.

The polarity of the backplane second, swap and execute signals can be
inverted by adding 1 to the SW361 setting. The clock phase can be
reversed by adding 2. The second signal can be changed to a 25ns pulse
by adding 4.

MASTER/SLAVE OPERATION

To change a board to slave operation, add 8 to the setting of the left
switch (SW360). It will then power up with the upper LED on to indicate
slave mode.

There should be no backplane signals from a slave board when no input is
applied.

To connect a master board, plug the RJ45 connectors of the supplied
cable in the upper RJ45 connector ('LVDS IN') of the slave board, and
the one below that on the master ('LVDS OUT' on Issue A, 'LVDS: OUT #1'
on Issue B boards). Designation J198/J199 on Issue A, J180/J181 on
Issue B.

The lower LED should then flash in synchronism with that on the master
board, and the backplane will be driven.

OTHER JUMPERS

The JP20n block at the top of the board must have links fitted at
positions 2 and 5.

The JP102 block should have 4 jumpers fitted vertically for the serial
ports to work with a PC thro 1 to 1 cables.

Serial Interface Protocol (Note: this is mostly still valid. Nathaniel 07/03)

for Calibration Detector TRC
C.Perry 06apr01, 10aug01

RS232 protocol: 8 data bits, no parity, 1 stop bit, 9600 baud.

Set/Clear/Query/Function
100./110./011.

A       a       1       SWAP rate 1
B       b       2       SWAP rate 2
                                swap period (full period, between interrupts is half this):
                                0: 200ms        1: 100ms        2: 50ms 3: 20ms

C       c       3       XQT rate 1
D       d       4       XQT rate 2
                                interval between executes:
                                0: 0.1ms        1: 1ms          2: 10ms 3: 100ms

E       e       5       XQT num 1
F       f       6       XQT num 2
                                number of executes in burst:
                                0: 2            1: 10           2: 100 3: 1000

G       g       7       XQT mode 1
H       h       8       XQT mode 2
                                mode of execute generation:
                                0: single       1: continuous   2: burst        3: synch burst

I i 9 XQT run
0: stop/reset 1: run (on transition for single)

J j : XQT status (query only)
0: stopped 1: running

K k ; SWAP run
0: stop/reset 1: run (acts at next second)

L l < SWAP status (query only)
0: stopped 1: running

M m = Timing run
0: stop/reset 1: run (acts @ next serial pulse in, or 2s)

N n > Timing status (query only)
0: stopped 1: running

"Set" sets a control bit; "clear" clears it. Where appropriate, bit weight
is given as 1 or 2. Character is echoed.

"Query" causes the "set" or "clear" code to be returned, according to the
current state. These codes are defined, but are not really needed (except
"XQT status").

Master-Slave TRC-to-TRC timing cable:

About the RJ-45 connectors (wiring pinouts):
Numbering the contacts in order from one end, the pairs are 1-2, 4-5,
7-8, 3-6. That is, three pairs each use two adjacent contacts, and the
other pair uses the contacts in between . This is the EIA T568
patterns; the A and B versions differ only in their color coding, which
I assume you don't care about.

You need to be careful about the type of cable. The ideal is a screened
Cat 5 cable. You can get away with a lower standard cable provided it
is intended for data. Audio, telephone or instrumentation twisted pair
cable may not work.

The longer the cable, the more critical its performance. Since I
imagine the length needed is more than the 10m used at CERN, it needs to
be reasonably good. Any networking cable should be ok. If necessary,
you ought to be ok with unscreened if that's all you can find, so long
as you try to keep it clear of noise sources. Better that, than a cable
that is too lossy at high frequencies, or does not have a proper
impedance.

Note that a long cable will make the slave outputs occur later than the
master. I set a fixed compensation in the firmware to suit 10m of
cable.

Nathaniel Tagg n.tagg1@physics.ox.ac.uk